--
-- VHDL Architecture ARMa_lib.ZeroExt.behav
--
-- Created:
--          by - Administrator.UNKNOWN (ECE-5BF87F3CFF5)
--          at - 03:53:22 10/26/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

LIBRARY ARMa_lib;
USE ARMa_lib.ARMa_types.all;

ENTITY ZeroExt IS
   PORT( 
      clk     : IN     std_logic;
      ADJ8out : OUT    ARMa_word;
      imm8    : IN     ARMa_imm8
   );

-- Declarations

END ZeroExt ;

--
ARCHITECTURE behav OF ZeroExt IS
BEGIN
  ADJ8out <= "000000000000000000000000" & imm8 after delay_MUX2;
  
END ARCHITECTURE behav;